1. Field of the Invention
The present invention relates to a transistor operating at a low power supply voltage by dynamically varying a threshold value, a semiconductor device including such transistors, and a method for producing such a semiconductor device. The present invention also relates to a contact formation technique for the transistors and an element separation technique suitable for integration of the transistor elements.
2. Description of the Related Art
The power consumption of a circuit, in which MOS transistors of different conductivity types are complementarily connected to each other (a CMOS circuit), increases in proportion to the square of a power supply voltage. Therefore, it is effective to reduce the power supply voltage for reduction of the power consumption of a large scale integrated circuit (LSI) formed by using CMOS circuits. However, since the driving power of transistors is reduced simultaneously with the reduction of the power supply voltage, the delay time of the LSI circuit is disadvantageously increased. The delay time is increased as the power supply voltage is lowered. In particular, it is known that, when a power supply voltage becomes lower than three times as much as a threshold voltage (i.e., 3xc3x97Vth), the delay time remarkably increases.
As a method for solving this problem, it is conceived to set a threshold voltage of the transistor to be low. However, if a threshold voltage is set at a low value, there arises a problem that a leak current during gate-OFF increases. Accordingly, the lower limit of the threshold voltage is limited depending on the acceptable degree of an OFF current (leak current).
In order to alleviate this problem, a dynamic threshold voltage operating transistor for effectively lowering a threshold voltage during gate ON has been proposed as a transistor corresponding to a low power supply voltage (A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation, F. Assaderaghi et al., IEDM94 Ext. Abst. pp.809).
A conventional structure of such a transistor is shown in FIG. 53. Although an N-channel MOS transistor (NMOS) is shown in FIG. 53, it is possible to construct a P-channel MOS transistor (PMOS) by providing an opposite polarity for the respective regions. This transistor is built on a Silicon-On-Insulator (SOI) substrate. A gate electrode and the substrate (a region of a silicon layer) are short-circuited through a local wiring by using an oversized metal wiring. In such a structure where the gate electrode and the substrate are short-circuited, when a bias voltage (a gate bias) is applied to the gate electrode, a forward bias as large as the gate bias is applied to an active region of the substrate.
However, in order to restrain the standby current in such a structure, the voltage to be applied to the gate electrode should be limited to below 0.6 V at which a lateral parasitic bipolar transistor is turned ON. In this manner, the same bias state as that in a normal transistor is formed during gate-OFF, and the substrate is forward biased as the gate bias increases during gate ON. As a result, a threshold voltage is reduced during gate ON.
As a result, the leak current during gate-substrate bias OFF is the same as that in a normal SOI transistor in the same channel state. When the transistor is an ON state, the threshold voltage is lowered as the gate-substrate bias is increased. Thus, the gate overdrive effect is increased to remarkably increase the driving power. A mobility is prevented from being deteriorated by the restraint of a longitudinal electric field on the surface of the substrate, which serves to increase the driving power. Since a lateral parasitic bipolar transistor is in an OFF state, the standby current is prevented from being remarkably increased.
Since the SOI substrate is utilized in the conventional technique described above, an active layer substrate is perfectly electrically insulated. Therefore, as compared with a device formed on a bulk substrate, holes generated in a channel (electrons in the case of a PMOS) are likely to be accumulated. As a result, the generation of kink in a drain current due to a substrate floating effect or characteristic hysteresis effect becomes a problem.
Moreover, the electrical insulation of the active layer substrate creates the problem of charge-up or causes electrostatic damage (ESD) to be generated during the fabrication process.
Furthermore, in the case where a separation by implanted oxygen (SIMOX) substrate, which has the best crystallinity at present, is used instead of the SOI substrate, the deterioration of characteristics due to carrier implantation to the bottom interface or capture becomes a problem. This is because the interface between the buried oxide film and the substrate has a larger degree of disturbance of the bonding state than that in the interface between the gate oxide film and the substrate on the channel side.
Furthermore, since a body (channel region) has an extremely small thickness (about 50 nm to about 200 nm) with the SOI substrate, the resistance becomes remarkably high. Therefore, even if the gate and the body are to be short-circuited by a contact region, it becomes more difficult to transfer a potential to the body as the distance from the contact increases. Therefore, the effect of a DTMOS is not fully demonstrated.
A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the plurality of shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the shallow well regions, and the shallow well region is electrically separated from the adjacent shallow well region.
According to another aspect of the present invention, a semiconductor device includes: a semiconductor substrate; a deep well region of a first conductivity type formed in the semiconductor substrate, which is capable of functioning as an emitter or a collector of a bipolar transistor; a shallow well region of a second conductivity type formed in the deep well region, which is capable of functioning as a base of the bipolar transistor; a source region and a drain region of the first conductivity type, formed in the shallow well region, which are capable of functioning as the collector or the emitter of the bipolar transistor; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to the shallow well region, and the semiconductor device is operated by a combination of an operation of a MOS transistor and an operation of the bipolar transistor.
In one embodiment of the invention, the adjacent shallow well regions are separated from each other by a groove type element separation structure which is deeper than the shallow well region and shallower than the deep well region.
In another embodiment of the invention, a field oxide film is formed so as to partially cover a region surrounded by the groove type element separation structure, and a contact region for electrically connecting the gate electrode and the shallow well region with each other is surrounded by the field oxide film.
In still another embodiment of the invention, the gate electrode includes a polycrystalline silicon film formed on the gate insulating film and a metal silicide film formed on the polycrystalline silicon film, and wherein the metal silicide film is electrically connected to the shallow well region via the contact region of the shallow well region, a high concentration impurity diffusion region, in which an impurity of the same conductivity type as that of the shallow well region is diffused at a higher concentration than that of a reminder of the shallow well region, is formed in the contact region, and an Ohmic contact is formed between the metal silicide film and the shallow well region through the high concentration impurity diffusion region.
In yet another embodiment of the invention, a semiconductor device further includes an interlayer insulating film and an upper wiring provided on the interlayer insulating film, wherein a contact hole is formed in the interlayer insulating film, which penetrates through the gate electrode and the gate insulating film so as to reach the contact region of the shallow well region, wherein a high concentration impurity diffusion region, in which an impurity of the same conductivity type as that of the shallow well region is diffused at a higher concentration than that of a remainder of the shallow well region, is formed in the contact region, an Ohmic contact is formed between the upper wiring and the shallow well region through the high concentration impurity diffusion region on the bottom of the contact hole, and wherein an Ohmic contact is formed between the gate electrode and the upper wiring on a side wall region of the contact hole.
According to still another aspect of the invention, a method for fabricating a semiconductor device including: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the plurality of shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to corresponding one of the shallow well regions, and the shallow well region is electrically separated from the adjacent shallow well region, the method includes the steps of: forming a side wall spacer on a side wall of the gate electrode; forming a contact hole in the gate electrode, for partially exposing a surface of the shallow well region in a contact region for connecting the shallow well region and the gate electrode with each other; depositing a refractory metal film so as to cover the gate electrode and the contact region in the shallow well region, which is partially exposed through the contact hole; and performing silicidation for part of the refractory metal film so as to form a refractory metal silicide film on the gate electrode and the contact region in a self-aligned manner.
In one embodiment of the invention, a method for fabricating a semiconductor device further includes the step of implanting impurity ions having the same conductivity type as that of the shallow well region through the contact hole into the shallow well region by ion implantation prior to or after the step of forming the refractory metal silicide film.
According to still another embodiment of the invention, a semiconductor device includes: a semiconductor substrate; a deep n-type well region formed in the semiconductor substrate; a deep p-type well region formed in the semiconductor substrate; a shallow p-type well region formed in the deep n-type well region; a shallow n-type well region formed in the deep p-type well region; an N-channel MOS transistor formed in the shallow p-type well region; and a P-channel MOS transistor formed in the shallow n-type well region, wherein the N-channel MOS transistor includes an n-type source region and an n-type drain region formed in the shallow p-type well region, a channel region formed between the n-type source region and the n-type drain region, a gate insulating film formed on the channel region, and an n-type gate electrode formed on the gate insulating film, wherein the P-channel MOS transistor includes a p-type source region and a p-type drain region formed in the shallow n-type well region, a channel region formed between the p-type source region and the p-type drain region, a gate insulating film formed on the channel region, and a p-type gate electrode formed on the gate insulating film, and wherein the n-type gate electrode is electrically connected to the shallow p-type well region, and the p-type gate electrode is electrically connected to the shallow n-type region.
In one embodiment of the invention, a semiconductor device further includes: a second n-type well region surrounding the deep p-type well region, which is deeper than the deep p-type well region; a second p-type well region surrounding the deep n-type well region, which is deeper than the deep n-type well region; and a groove type element separation structure for separating the second n-type well region and the second p-type well region from each other.
In another embodiment of the invention, a difference of a potential formed between the shallow well region and the source region and a difference of a potential formed between the shallow well region and the drain region is set so as to be smaller than a built-in potential of a pn junction in the semiconductor device during operation.
In still another embodiment of the invention, a method includes the steps of: forming a side wall spacer on a side wall of each of the n-type gate electrode and the p-type gate electrode; forming a first contact hole in the n-type gate electrode for partially exposing a surface of the shallow p-type well region in a first contact region for connecting the shallow p-type well region and the n-type gate electrode with each other, and for forming a second contact hole in the p-type gate electrode for partially exposing a surface of the shallow n-type well region in a second contact region for connecting the shallow n-type region and the p-type gate electrode with each other; depositing a refractory metal film so as to cover the n-type gate electrode, the p-type gate electrode and the first contact region in the shallow p-type well region and the second contact region in the shallow n-type well region; and performing silicidation for part of the refractory metal film so as to form a refractory metal silicide film on the n-type gate electrode, the p-type gate electrode, the first contact region and the second contact region in a self-aligned manner, wherein, upon implantation of a p-type impurity ion for forming the p-type source region and the p-type drain region, the p-type impurity ion is implanted into the first contact region, and upon implantation of an n-type impurity ion for forming the n-type source region and the n-type drain region, the n-type impurity ion is implanted into the second contact region.
In yet another embodiment of the invention, the gate electrode is electrically connected to the shallow well region via a source region or a drain region of a MOS transistor, and a constant voltage is applied to a gate electrode of the MOS transistor.
In yet another embodiment of the invention, the gate electrode is electrically connected to the shallow well region via a second source region or a second drain region of a second MOS transistor, and the drain region is connected to a second gate electrode of the second MOS transistor.
According to still another aspect of the invention, a semiconductor device includes: a semiconductor substrate; an n-type deep well region formed in the semiconductor substrate, which is capable of functioning as an emitter or a collector of an NPN type bipolar transistor; a p-type shallow well region formed in the n-type deep well region, which is capable of functioning as a base of the NPN type bipolar transistor; an n-type source region and an n-type drain region formed in the p-type shallow well region, which are capable of functioning as the collector or the emitter of the NPN type bipolar transistor; a channel region formed between the n-type source region and the n-type drain region; a gate insulating film formed on the channel region; an n-type gate electrode formed on the gate insulating film; a p-type deep well region formed in the semiconductor substrate, capable of functioning as an emitter or a collector of a PNP type bipolar transistor; an n-type shallow well region formed in the p-type deep well region, capable of functioning as a base of the PNP bipolar transistor; a p-type source region and a p-type drain region formed in the n-type shallow well region, which are capable of functioning as the collector or the emitter of the PNP bipolar transistor; a channel region formed between the p-type source region and the p-type drain region; a gate insulating film formed on the channel region; and a p-type gate electrode formed on the gate insulating film, wherein the n-type gate electrode is electrically connected to the p-type shallow well region via source/drain regions of a first MOS transistor while the n-type drain region is electrically connected to a gate electrode of the first MOS transistor, the p-type gate electrode is electrically connected to the n-type shallow well region via source/drain regions of a second MOS transistor while the p-type drain region is electrically connected to a gate electrode of the second MOS transistor, and wherein the semiconductor device further comprises a p-type deeper well region which is deeper than the n-type deep well region, including the n-type deeper well region, and a n-type deeper well region which is deeper than the p-type deep well region, including the p-type deep well region, a potential of the n-type deep well region and a potential of the p-type deeper well region are set to be identical to each other, and a potential of the p-type deep well region and a potential of the n-type deeper well region are set to be identical to each other.
In one embodiment of the invention, a junction between the source/drain regions, and the shallow well region, is doped with nitrogen ions or carbon ions.
In another embodiment of the invention, a semiconductor device includes a power supply voltage blocking circuit between a circuit block constituted by using the semiconductor device and a power supply voltage source, wherein supply of a power supply voltage is blocked when the circuit block is in a standby state.
In still another embodiment of the invention, a semiconductor device includes a block circuit between a circuit block constituted by using the semiconductor device and a power supply voltage source, another block circuit between the circuit block and a ground voltage supply source, wherein supply of a power supply voltage and supply of a ground voltage are blocked when the circuit block is in a standby state.
According to yet another embodiment of the invention, a method for fabricating a semiconductor device includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the plurality of shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the shallow well regions, and the shallow well region is electrically separated from the adjacent shallow well region, the method includes the step of: forming a groove type element separation structure for separating the shallow well regions from each other and a field oxide film prior to the formation of the shallow well regions.
According to yet another embodiment of the invention, a semiconductor device includes: a semiconductor substrate; a plurality of transistor elements formed in the semiconductor substrate; and a groove type element separation structure for separating the plurality of transistor elements from each other, wherein the groove type element separation structure includes a groove formed in the semiconductor substrate, an insulating layer formed along an inner wall of the groove, and a silicon film filling the groove, and a field oxide film having a bird""s beak is formed above the groove in an edge portion of an opening of the groove.
In one embodiment of the invention, the semiconductor substrate includes a first semiconductor layer of the first conductivity type and a second semiconductor layer of the second conductivity type positioned below the first semiconductor layer, a bottom of the groove extends from a surface of the semiconductor substrate to reach a middle of the second semiconductor layer, and a high concentration region, in which an impurity of the second conductivity type is diffused at a higher concentration than the other region, is formed in the vicinity of the bottom of the groove.
In another embodiment of the invention, a concentration of the impurity of the second conductivity type in the high concentration region is in the range of about 1xc3x971018/cm3 to about 1xc3x971019/cm3.
According to yet another aspect of the invention, a method for fabricating a semiconductor device including a plurality of transistor elements formed in a semiconductor substrate and an element separation structure for separating the plurality of transistor elements from each other, the method includes the steps of: forming a groove in the semiconductor substrate; forming an insulating layer along an inner wall of the groove; filling the groove with a polycrystalline silicon film; forming an anti-oxidation mask selectively covering an element region where the transistor elements are to be formed; and simultaneously oxidizing a surface of the polycrystalline silicon film filling the groove and an exposed surface of the semiconductor substrate so as to form an element separation structure including the groove and a field oxide film.
In one embodiment of the invention, the step of forming the groove includes the steps of: forming a first silicon oxide film on the semiconductor substrate; depositing a first silicon nitride film on the first silicon oxide film; and successively etching the first silicon nitride film, the first silicon oxide film, and the semiconductor substrate positioned on a region where the groove is to be formed so as to form the groove.
In another embodiment of the invention, the step of forming the insulating layer along the inner wall of the groove includes the step of forming a second silicon oxide film along the inner wall of the groove.
In still another embodiment of the invention, the step of filling the groove with the polycrystalline silicon film includes the step of depositing the polycrystalline silicon film so as to fill the groove and the step of selectively etching back the polycrystalline silicon film.
In yet another embodiment of the invention, the step of forming the anti-oxidation mask includes the step of selectively removing the first silicon nitride film positioned in a field region of the semiconductor substrate so as to form the anti-oxidation film from a remaining portion of the first silicon nitride film.
In yet another embodiment of the invention, the step of forming the anti-oxidation mask includes the steps of: depositing a second silicon nitride film after the step of filling the groove with the polycrystalline silicon film; and selectively removing the first silicon nitride film and the second silicon nitride film positioned in a field region of the semiconductor substrate so as to form the anti-oxide mask from a remaining region of the first silicon nitride film and the second nitride film.
In yet another embodiment of the invention, the second silicon nitride film is changed to be a third oxide film by the thermal oxidation in the step of forming the element separation structure.
In yet another embodiment of the invention, the step of forming the groove includes the steps of: forming a first silicon oxide film on the semiconductor substrate; depositing a first silicon nitride film on the first silicon oxide film; depositing a second silicon oxide film on the first silicon nitride film; and successively etching the second silicon oxide film, the first silicon nitride film, the first silicon oxide film and the semiconductor substrate which are positioned in a region where the groove is to be formed.
In yet another embodiment of the invention, the step of forming the anti-oxidation mask includes the steps of: removing the second silicon oxide film; and selectively removing the first silicon nitride film positioned in a field region of the semiconductor substrate so as to form the anti-oxidation mask from a remaining portion of the first silicon nitride film.
In yet another embodiment of the invention, the step of forming the anti-oxidation mask includes the steps of: removing the second silicon oxide film; depositing a second silicon nitride film; and selectively removing the first silicon nitride film and the second silicon nitride film positioned in a field region of the semiconductor substrate so as to form the anti-oxidation mask from a remaining portion of the first silicon nitride film and the second silicon nitride film.
In yet another embodiment of the invention, the step of forming the anti-oxidation mask includes the step of: selectively removing the second silicon oxide film and the first silicon nitride film positioned in a field region of the semiconductor substrate so as to form the anti-oxidation mask from a remaining portion of the second silicon oxide film and the first silicon nitride film.
In yet another embodiment of the invention, the step of forming the anti-oxidation mask includes the steps of: depositing a second silicon nitride film after the step of filling the groove with the polycrystalline silicon film; and selectively removing the second silicon nitride film, the second silicon oxide film and the first silicon nitride film positioned in a field region of the semiconductor substrate so as to form the anti-oxidation film from a remaining portion of the second silicon nitride film, the second silicon oxide film and the first silicon nitride film.
In yet another embodiment of the invention, the method for fabricating a semiconductor device includes the step of depositing a third silicon oxide film so as to cover the first silicon nitride film and the second silicon oxide film formed in the groove after the formation of the second silicon oxide film and prior to the step of filling the groove with the polycrystalline silicon film, wherein a portion positioned in a region of the third silicon oxide film excluding the groove is etched in the step of filling the groove with the polycrystalline silicon film.
In yet another embodiment of the invention, the step of forming the anti-oxidation mask includes the steps of: depositing a second silicon nitride film after the step of etching the third silicon oxide film; selectively removing the first silicon nitride film and the second silicon nitride film positioned in a field region of the semiconductor substrate so as to form the anti-oxidation mask from a remaining portion of the first silicon nitride film and the second silicon nitride film.
In yet another embodiment of the invention, the second silicon nitride film is changed to be a fourth oxide film by the thermal treatment in the step of forming the element separation structure.
In yet another embodiment of the invention, the method for fabricating a semiconductor device includes the step of depositing a third silicon oxide film so as to cover the first silicon nitride film and the second silicon oxide film formed in the groove after the formation of the second silicon oxide film and prior to the step of filling the groove with the polycrystalline silicon film, and wherein the step of forming the anti-oxidation mask includes the step of etching a region of the third silicon oxide film and a region of the first silicon nitride film positioned in a field region of the semiconductor substrate after the step of filling the groove with the polycrystalline silicon film and prior to the step of forming the element separation structure.
In yet another embodiment of the invention, a method for fabricating a semiconductor device includes the step of depositing a third silicon oxide film so as to cover the first silicon nitride film and the second silicon oxide film formed in the groove after the formation of the second silicon oxide film and prior to the step of filling the groove with the polycrystalline silicon film, wherein the step of forming the anti-oxidation mask includes the steps of: depositing a second silicon nitride film after the step of filling the groove with the polycrystalline silicon film; and selectively removing the second silicon nitride film, the third silicon oxide film and the first silicon nitride film positioned in a field region of the semiconductor substrate so as to form the anti-oxidation mask from a remaining portion of the second silicon nitride film, the third silicon oxide film and the first silicon nitride film.
In one embodiment of the invention, a method for fabricating a semiconductor device includes the step of implanting an impurity ion into a bottom of the groove between the step of forming the groove in the semiconductor substrate and the step of filling the groove with the polycrystalline silicon film.
According to still another aspect of the invention, a field effect transistor device includes: a deep well region of a first conductivity type formed in a semiconductor substrate; at least one shallow well region of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type formed in the shallow well region; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to the shallow well region.
Thus, the invention described herein makes possible the advantages of: (1) providing a semiconductor device having a dynamically varying threshold, capable of operating at a low voltage; and (2) providing a method for fabricating such a semiconductor device.